Setup Xilinx ISE 14.1 (Free Version) and Digilent’s Adept Utilities in Fedora 17 64-bit

Hello everybody! As promised in the previous post, I’m going to show you how to setup the tools you’ll need to work with Digilent’s FPGA boards. This tutorial is also helpful if you want to use Xilinx ISE in Fedora. It is possible to program a number of boards (including the Nexys3 which I have) directly from Xilinx.

There was no real problem for me for most of the installation phase. Things worked great till the cable drivers installation. No matter what I tried, it wouldn’t work. After searching a lot online, I saw that this is a problem on RedHat and Centos as well (please correct me if I am wrong). After more searching, I found out how I can get things to work. I’m actually redoing the entire installation so that I don’t miss any step. So lets get started! πŸ™‚ Read more of this post

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New Equipment! An FPGA Board And Some Delicious Pi :-)

So I’ve finally got myself something I’ve been wanting for a long time – an FPGA board. FPGAs are extremely useful for building large digital systems. All you need to do is write code in either VHDL or Verilog and you’re done (well not quite. There are a few more steps but we’ll look at that later). Originally, I was planning to buy a DSP board from Texas Instruments. However, a friend at MITx (More on that in another blog post) told me about the boards made by Digilent (Thanks Hobie!). Till now, the boards I found were too costly for me. There were a few with Digilent that were perfect! I decided to go with the Nexys3. Read more of this post

VHDL in Alliance – Behavioral Simulations

Hello everyone and welcome to the second tutorial on the Alliance VLSI package! πŸ™‚ Here we will look at how we can build a digital system using a behavioral model and simulate the VHDL code we write. I hope you have read the previous tutorial on genpat. We will need what ever we learn there to test the code we write in this tutorial. I also assume that you are familiar with VHDL. Alright then. Lets begin!

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VHDL in Alliance – A Different Start!

Welcome back! πŸ™‚ Its time to start off with Digital Design in VHDL using the Alliance package available in Fedora Electronic Lab. Now most tutorials would start of with the simulator itself. I have however, chosen a different start – The stimulus. The reason for this it that we need a stimulus for every simulation that we run in future tutorials and Alliance uses a separate file format for this. Read more of this post

Verilog & VHDL up Next! – Warming up

Hello everyone!

Posting after ages since I’ve been quite busy at work. But I haven’t forgotten about this blog :). As promised, I will deal with some tools on HDLs next – namely Icarus Verilog and the Alliance VLSI CAD system (which uses VHDL).

This post is basically to help you get geared up. Most probably you won’t even need a tutorial after this. ;). Oh and before I begin, I finally bought an Android phone last month. Its an HTC Wildfire πŸ™‚

Not as powerful as a Nexus and many phones out there but it was worth it. Has a nice camera, supports most of the apps on the market.

Alright back to why I’m posting. Here is a small description of the stuff we will look at in the forthcoming posts:

  • Icarus Verilog: A Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. (Source: http://spins.fedoraproject.org/fel/#portfolio Couldn’t open the official site for some reason :-|)
  • Alliance: Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. (Source: http://www-asim.lip6.fr/recherche/alliance/)

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ngspice – Interactive Mode!

Welcome back for the 5th tutorial on SPICE in Fedora Electronic Lab. πŸ™‚ This time we’ll look at ngspice’s interactive mode. We’ll see what this means in some time. Before that, make sure that you have gone through the previous tutorials. These are all filed under the SPICE category (point your mouse to Tutorials, then click SPICE). We will reuse the example circuits we created in the previous tutorials for this one. I hope you’ve gone through those first. We’ll begin with two circuits to show how some simple analysis can be done just like in batch mode. Finally we’ll end with an example which shows a great aspect of the interactive simulations – tweaking circuits automatically.

Before we begin any circuit, delete the SPICE include symbol from the schematic and get the netlist again. We do not need the cmd files now. Alternatively you could just open the netlist and delete the .INCLUDE line. We will be looking at the Bridge Rectifier, the BJT Amplifier andΒ  the op-amp non-inverting amplifier. Now lets begin πŸ™‚

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Breaking it down – The .SUBCKT

Having done so many simulation examples, ever wondered how complex actual circuits can be? When you go on to design a circuit with some application it won’t be just one amplifier or one rectifier. It’ll have dozens of blocks. How do you fit all that in one schematic? Well you can’t – at least not without getting totally mixed up with where each block is. Thats where hierarchical design comes in. This means that you break down a system into blocks. Break these blocks down even further till you get the simplest ones – like a tree branching out and having leaves at the end. The advantage of this is that most of the time, these “leaves” will repeat across your circuit and with a hierarchical design, these circuits need to be defined just once and reused again.

I hope you have read my previous tutorial on symbol creation in gschem as well as other tutorials on SPICE. You can get these tutorials by pointing your mouse to the Tutorials menu at the top and then selecting SPICE. You need the symbol of the previous tutorial to go through this one. Click Here to go to the symbols creation tutorial.

We will first look at a few op-amp circuits. I will be using LM741 for the examples. You can get the model (and many others) from Texas Instruments. Next we’ll build a two-stage BJT amplifier using a single BJT amplifier as a building block. Just like last time, I will explain only what is new. So lets begin, with my favorite part of analog circuits – operational amplifiers πŸ™‚

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Creating Your Own Symbols in gschem

Before writing another tutorial on SPICE, I thought of spending some time on creating symbols. This will be necessary because we will be looking at op-amp circuits next. There are op-amps in the gschem library but there are incompatibilities between those and the model files which the manufacturers provide. While trying to figure out how to create symbols, I found an excellent 3 part tutorial on this. I will take you through the creation of an op-amp symbol in this tutorial but I still feel this video will do better than that. Take a look at these before reading on:

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Simulating Circuits – More Examples!

Hope you liked my previous tutorials on SPICE simulation in Fedora Electronic Lab. Well this post comes a little late because I had a lot of circuits in mind. So take a deep breadth and get ready for Part 3! πŸ™‚

I’m assuming that you’ve read through the previous two tutorials and that you are now comfortable with using gschem. After this tutorial, you must go through the ngspice manual atleast once. I’ll be moving a bit fast from now on because there is a lot to cover. If something is not clear, feel free to post a comment. I also assume that you’ve completed a course on analog electronic circuits. If you are currently in such a course, go through the circuits you are familiar with and come back later.

Remember to plan a directory structure before each example. Also, the models for the transistors are available from Fairchild Semiconductors and diodes from Diodes.com. I’m not posting these here due to copyright restrictions.

A quick recap:

  1. You draw you circuits in gschem.
  2. Generate the netlist by running: gnetlist -g spice-sdb -o <output_netlist.net> Β <input_schematic.sch>
  3. Always check the netlist once yourself. Also see which are the input and output nodes.
  4. Simulate the circuit using: ngspice -b -r <raw_file.raw> -o <log_file.log> <netlist.net>
  5. Finally open the waveform viewer by running gwave <raw_file.raw> and dragging the output you want to see to the panel.

Ready? Go! Read more of this post

Simulating Circuits in the CLI

My previous tutorial on EDA in FEL showed you how to simulate circuits using gspiceui with the gnucap simulator. This time I’ll show you to do the same using the command line interface (CLI) with the ngspice simulator. I had a few doubts regarding the use of ngspice and got them cleared in FEL mailing lists. We’ll not look at gnucap for now because I have to learn to use it myself. Alright so lets begin! πŸ™‚

Prerequisites and References

These are the same as https://ashwith.wordpress.com/2010/09/10/circuit-simulation-in-gnulinux-lets-begin/

Do go through that tutorial first if you haven’t already.

In addition to this, you need to be familiar with SPICE netlists. Check the ngspice manual. It has a well explained, detailed description with a few examples in the end. To get started quickly go through this tutorial http://www.seas.upenn.edu/~jan/spice/spice.overview.html

I got some help with ngspice at the FEL mailing list as well. You can sign up here Β https://admin.fedoraproject.org/mailman/listinfo/electronic-lab.

gschem > gnetlist > ngspice > gwave

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