VHDL in Alliance – Behavioral Simulations


Hello everyone and welcome to the second tutorial on the Alliance VLSI package! 🙂 Here we will look at how we can build a digital system using a behavioral model and simulate the VHDL code we write. I hope you have read the previous tutorial on genpat. We will need what ever we learn there to test the code we write in this tutorial. I also assume that you are familiar with VHDL. Alright then. Lets begin!

Example 1  – The J K Flip Flop

Pretty simple code. Here it is:

library ieee;
use ieee.std_logic_1164.all;

entity jk_ff is
port
(
 clk  : in  std_logic;
 J    : in  std_logic;
 K    : in  std_logic;
 Q    : out std_logic;
 Qbar : out std_logic
);
end jk_ff;

architecture jk_ff_behavioral of jk_ff is
begin
 process(clk)
 variable Q_temp, Qbar_temp : std_logic;
 variable JK_temp : std_logic_vector (1 downto 0) := "00";
 begin

 if rising_edge(clk) then
  JK_temp := (J & K);
  case JK_temp is
   when "00"   => Q_temp := Q_temp;
   when "01"   => Q_temp := '0';
   when "10"   => Q_temp := '1';
   when "11"   => Q_temp := not Q_temp;
   when others => Q_temp := Q_temp;
  end case;
  Q         <= Q_temp;
  Qbar_temp := not Q_temp;
  Qbar      <= Qbar_temp;
  end if;

 end process;

end jk_ff_behavioral;

Save this to a file named jk_ff.vhdl and run the command:

vasy -Vao jk_ff

First, notice that we have, again, left out the file extension. Now some information on that command. The Alliance simulator can understand only a subset of the VHDL language. Many of the statements in our code may not belong to that subset. The program vasy converts your VHDL code to the subset which Alliance understands. vasy will generate a file called jk_ff.vbe. Have a look at it if you like. If you want more information on vasy, look up the man page. Next we need a stimulus so here is the genpat program (which we looked at in the previous tutorial):

#include <stdio.h>
#include "genpat.h"

char *inttostr(entier)
int entier;
{
 char *str;
 str = (char*) mbkalloc(32 * sizeof (char));
 sprintf(str, "%d", entier);
 return(str);
}

main()
{
 int temp_clk, temp_J, temp_K, time_tick, counter;
 int i;

 DEF_GENPAT("jk_ff");

 DECLAR("clk", ":2", "B", IN, "", "");
 DECLAR("J", ":2", "B", IN, "", "");
 DECLAR("K", ":2", "B", IN, "", "");
 DECLAR("Q", ":2", "B", OUT, "", "");
 DECLAR("Qbar", ":2", "B", OUT, "", "");

 temp_clk = 0;
 time_tick = 0;
 counter = 1;
 temp_J = 1;
 temp_K = 0;
 SETTUNIT("ps");
 for(i = 0; i < 16; i++)
 {
  AFFECT(inttostr(time_tick), "clk", inttostr(temp_clk));
  AFFECT(inttostr(time_tick), "J", inttostr(temp_J));
  AFFECT(inttostr(time_tick), "K", inttostr(temp_K));

  if(temp_clk == 0)
   temp_clk = 1;
  else
   temp_clk = 0;

  if(counter%2 == 0)
  {
   if(temp_J == 0)
    temp_J = 1;
   else
    temp_J = 0;
  }

  if(counter%4 == 0)
  {
   if(temp_K == 0)
    temp_K = 1;
   else
    temp_K = 0;
  }

  time_tick = time_tick + 10;
  counter++;

 }
 SAV_GENPAT();

}

Generate the patterns file using the command:

genpat jk_ff

Finally call the simulator by running the command:

asimut -b jk_ff jk_ff jk_ff_out

asimut is the name of the simulator program. The -b option tells asimut that we have used behavioral code. The first jk_ff refers to jk_ff.vbe and the second refers to jk_ff.pat. The last argument is the file where we would like our result. This file is also a patterns file and will be generated by asimut once the simulation completes. Lets have a look at this file. First run:

xpat &

Now go to File > Open. Select jk_ff_out.pat and click OK. Here is what you should see.

Simple isn’t it? We’ll look at 3 more examples quickly.

Example 2 – A 4×1 Multiplexer

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;

entity mux4x1 is
port  ( I0  : in  std_logic;
 I1  : in  std_logic;
 I2  : in  std_logic;
 I3  : in  std_logic;
 En  : in  std_logic;
 Sel : in  std_logic_vector (1 downto 0);

 Y   : out std_logic
 );
end mux4x1;

architecture mux4x1_behavioral of mux4x1 is
begin
 process(I0, I1, I2, I3, En, Sel)
  variable y_out : std_logic;
 begin
  if(En = '1') then
   case Sel is
    when "00" => y_out := I0;
    when "01" => y_out := I1;
    when "10" => y_out := I2;
    when "11" => y_out := I3;
   end case;
   Y <= y_out;
  else
   Y <= '0';
  end if;
 end process;
end mux4x1_behavioral;

Save this to mux4x1.vhdl. Patterns File:

--port list
--inputs
in      I3                B;;;
in      I2                B;;;
in      I1                B;;;
in      I0                B;;;
in      En                B;;;
in      Sel (1 downto 0)  B;;;
--output
out     Y                 B;;;

begin
--Signal List
--          I I I I E  S Y
--          3 2 1 0 n  e
--                     l

<   0ns>  : 0 0 0 0 0 00 ?* ;
< +50ns>  : 0 0 0 1 1 00 ?* ;
< +50ns>  : 1 1 1 0 1 00 ?* ;
< +50ns>  : 0 0 1 0 1 01 ?* ;
< +50ns>  : 1 1 0 1 1 01 ?* ;
< +50ns>  : 0 1 0 0 1 10 ?* ;
< +50ns>  : 1 0 1 1 1 10 ?* ;
< +50ns>  : 1 0 0 0 1 11 ?* ;
< +50ns>  : 0 1 1 1 1 11 ?* ;
< +50ns>  : 0 0 0 0 0 00 ?* ;

end;

I didn’t write a program here since the pattern was simple enough. If you understood the genpat tutorial, it shouldn’t be hard to understand what the format is. The extra semicolons in the port declarations refer to the extra spaces (“:nb_space” in DECLAR). Save this to mux4x1.pat. Finally run these commands:

vasy -Vao mux4x1
asimut -b mux4x1 mux4x1 mux4x1_out
xpat &

And open mux4x1_out.pat. This is the waveform you should see:

Example 3 – A Modulo 8 Counter

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is
port
(
 clk : in  std_logic;
 rst : in  std_logic;
 Q   : out std_logic_vector (2 downto 0)
);
end counter;

architecture counter_behavioral of counter is
begin
  process(clk)
    variable q_temp : unsigned (2 downto 0);
  begin
    if rising_edge(clk) then
      if rst = '1' then
        q_temp := "000";
      else
        q_temp := q_temp + 1;
      end if;
    end if;
    Q <= std_logic_vector(q_temp);
  end process;
end counter_behavioral;

Save this to counter.vhdl. Patterns file:

--port list
--inputs
in       clk B;;;
in       rst B;;;
--outputs
out      Q (2 downto 0) B;;;

begin
--Signal list
--           c r Q
--           l s  
--           k t

<   0 ps>  : 0 1 *** ;
< +10 ps>  : 1 1 *** ;
< +10 ps>  : 0 1 *** ;
< +10 ps>  : 1 1 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
< +10 ps>  : 1 0 *** ;
< +10 ps>  : 0 0 *** ;
end;

Wrote this myself as well. It is long but pretty straight forward since the clock keeps toggling and the reset is held high only initially. You may prefer to pull up the reset in the middle to see if it is working. Save it to counter.pat. Now run

vasy -Vao counter
asimut -b counter counter counter_out
xpat &

Open counter_out.pat and have a look at the output:

Final example! Here we have a few interesting things to look at 🙂

Example 4 – 4 bit Adder

VHDL Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder_4 is
port
(
 A     : in  std_logic_vector (3 downto 0);
 B     : in  std_logic_vector (3 downto 0);
 Cin   : in  std_logic;
 Sum   : out std_logic_vector (3 downto 0);
 Cout  : out std_logic
);
end adder_4;

architecture adder_4_behavioral of adder_4 is
begin
  process(A, B, Cin)
    variable Sum_temp : unsigned (4 downto 0);
    variable Cin_temp : unsigned (4 downto 0);
  begin
    Cin_temp    := "00000";
    Cin_temp(0) := Cin;
    Sum_temp    := unsigned(A) + unsigned(B) + Cin_temp;
    Cout        <= Sum_temp(4);
    Sum         <= std_logic_vector(Sum_temp(3 downto 0));
  end process;
end adder_4_behavioral;

Save it to adder_4.vhdl. This time we will write a genpat program. Here is the code:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include "genpat.h"
char *inttostr(entier)
int entier;
{
 char *str;
 str = (char*) mbkalloc(32 * sizeof (char));
 sprintf(str, "%d", entier);
 return(str);
}

main()
{
 int temp_A, temp_B, temp_C, temp_Cin, temp_Sum, temp_Cout;
 int num_iterations, i;

 DEF_GENPAT("adder_4");

 DECLAR("A",     ":2", "X", IN,  "3 downto 0",  "");
 DECLAR("B",     ":2", "X", IN,  "3 downto 0",  "");
 DECLAR("Cin",   ":2", "B", IN , "",            "");
 DECLAR("Sum",   ":2", "X", OUT, "3 downto 0",  "");
 DECLAR("Cout",  ":2", "B", OUT, "",            "");

 srand(time(NULL));
 num_iterations = 100;

 for(i = 0; i < num_iterations; i++)
 {
  /*Generate Random Values for A B and Cin*/
  temp_A = rand() % 16;
  temp_B = rand() % 16;
  temp_Cin = rand() % 2;

  /*Calculate the Expected Sum and Cout*/
  temp_Sum = temp_A + temp_B + temp_Cin;
  temp_Cout = temp_Sum >> 4;

  /*Store it on the pattern signals*/
  AFFECT(inttostr((i*10)), "A", inttostr(temp_A));
  AFFECT(inttostr((i*10)), "B", inttostr(temp_B));
  AFFECT(inttostr((i*10)), "Cin", inttostr(temp_Cin));
  AFFECT(inttostr((i*10)), "Sum", inttostr(temp_Sum));
  AFFECT(inttostr((i*10)), "Cout", inttostr(temp_Cout));
 }
 SAV_GENPAT();
}

I hope you can see how genpat simplifies things now. We can easily generate random numbers in C. This is really useful when we need to test with a larger number of inputs. Also notice that we’ve used AFFECT on the outputs as well. This allows us to tell the simulator the outputs we expect from the system. If there is a mismatch, asimut will flag an error. Run the following commands:

genpat adder_4
vasy -Vao adder_4
asimut -b adder_4 adder_4 adder_4_out
xpat &

Here is my waveform. The waveform which you get will differ because of the randomization in inputs.

Now suppose we change a value in adder4.pat and cause the ouput to be incorrect, this is the error which the simulator will flag:

Error 113: expected value differs from the simulation's result on `cout`

Over here, I modified Cout and asimut signalled an error.

Well that’s it as far as behavioural simulations are concerned. Try some more examples yourself and do not forget to read the man pages. I hope I was able to make things clear. Do provide your feedback in the form of a comment. Thanks for reading! 🙂

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30 Responses to VHDL in Alliance – Behavioral Simulations

  1. Pingback: Tweets that mention VHDL in Alliance – Behavioral Simulations « Ashwith -- Topsy.com

  2. odev says:

    Hi Ashwith,
    Do you know if there is a way to work with Verilog on Alliance tools?
    If not, is there a recommended conversion path from Verilog to VHDL or any other Alliance supported format?
    Thanks for the great posts, keep them coming 🙂

    • Ashwith says:

      Hey!
      I know what you mean. I’ve been hunting for free software that can give me a GDSII like Alliance. Well Alliance doesn’t work directly with Verilog. Icarus Verilog does have a VHDL code generator however, so the most obvious thing to do is first run:

      iverilog -tvhdl -o vhdl_file.vhd verilog_file.v
      and then
      vasy -Vao vhdl_file
      and so on

      However, when I tried this approach on a simple design (an ALU), vasy crashed with a segmentation fault. So I’ve been relearning VHDL till I figure out something. Do let me know if you have any luck. 🙂 I’m glad you found these posts helpful 🙂

  3. Somebody out there says:

    Check: http://opencircuitdesign.com/verilog/index.html If you want a Verilog to GDS2 flow.

  4. gaffoor says:

    how to use genpat command in ubuntu, im unable to generate pat file, i refered using man page and used the command ” GenPat jkff_c jkff.vhdl jkff_in.pat “, i got generated .pat file but im unable to run ” asimut -b jkff jkff_in jkff_out “. It says

    initializing …
    searching `jkff` …
    BEH : Compiling `jkff.vbe` (Behaviour) …
    making GEX …

    searching pattern file : `jkff_in` …
    PAT : Error 99 line 1 : syntax error
    PAT : Error 99 line 2 : syntax error
    PAT : Error 99 line 4 : syntax error
    PAT : Error 99 line 8 : syntax error
    PAT : Error 99 line 9 : syntax error
    PAT : Error 99 line 10 : syntax error
    PAT : Error 99 line 11 : syntax error
    PAT : Error 99 line 13 : syntax error
    PAT : Error 99 line 15 : syntax error
    PAT : Error 99 line 19 : syntax error

    cannot continue further more.

    have a nice day…

    is that procedure is correct?

    Reply me to my mail id,

    • Ashwith says:

      Gaffor,

      That is not the way genpat is used. I think you are confused between the patterns generator and the simulator.

      You first right a C program. Then you use genpat to generate a patterns file (the one with the .pat extension).

      Now that you have the patterns file, you need to use the simulator, asimut, to run the simulation. However, you cannot use VHDL code with asimut since it supports only a subset of the language. So what you must to is use a program called Vasy. This converts the VHDL code to a .vbe file. This file also contains VHDL code but only the subset supported by asimut.

      Another thing to remember when you use the alliance CAD package is that you should specify only the filename in the parameters – no extension. For example if the file is “adder.vhdl”, the parameter to the command should be just “adder”.

      Hope this helps and Happy New Year! 🙂

  5. RAMKI says:

    Ashwith,

    How to use Structural code in Alliance Tools using terminal? I create .vst format and i am not get output ? In XPAT windows i select out .pat file it wont show my output … my program is correct .. then i check out again it wont show my output … how to rectifier this error? so Please help me…

    Thanks & Regards

    RAMKI

  6. RAMKI says:

    Ashwith,

    How to use fsm code in Alliance Tools using terminal? Is It any separate FSM code for suitable for alliance tools … Or Normally VHDL fsm code ? How sholud i create .fsm format ? So Please help me…

    file:///home/ramki/Videos/alliance_trace_graph.png

    In this link 1 flow chart is give is it correct ? For i am try .vbe , .vhdl format in get proper output for all steps… So how use for FSM code & FSM procedure (.fsm ) and also for structural procedure(.vst) tell me details … So please help me

    Thanks & Regards

    RAMKI

  7. RAMKI says:

    Thanks You Ashwith ……… 🙂

  8. RAMKI says:

    Ashwith how should i contact you ? any mail id have contact 2 you ? so please reply me …

    Thanks & Regards

    RAMKI

  9. RAMKI says:

    Good Evening Ashwith,
    In Alliance Structural(.vst) format we should write for test pattern code its compulsory or not ? ” http://www.cc.toin.ac.jp/sc/palacios/portal/books_e.html
    I saw this website it mention two book one of this -> Design of CMOS VLSI Circuits book . In this book chapter -2 its given some example for Structural format (.vst) it won’t mention the test pattern code its right or wrong ? If i follows that procedure its right or wrong can you please clarify me doubt Ashwith ….
    Right now I am working ALLIANCE TOOLS … So please help me…

    Thanks & Regards
    RAMKI

    • Ashwith says:

      Like I said before, I don’t know about structural modelling in Alliance unfortunately.

      I actually gave up because Asimut kept crashing when I tried to do a simple sim. It also didn’t work for a behavioral sim either. I filed two bugs on the Redhat bugzilla but it seems no one has been able to work on it yet. So I’ve stopped looking at Alliance for now (I am also not very comfortable with VHDL :-/ It’s different from most of the languages I know and it takes a while for me to get used to it.)

  10. RAMKI says:

    Good Evening Ashwith,
    In Alliance Structural(.vst) format we should write for test pattern code its compulsory or not ? ” http://www.cc.toin.ac.jp/sc/palacios/portal/books_e.html
    I saw this website it mention two book one of this -> Design of CMOS VLSI Circuits book . In this book chapter -2 its given some example for Structural format (.vst) it won’t mention the test pattern code its right or wrong ? If i follows that procedure its right or wrong can you please clarify me doubt Ashwith ….
    Right now I am working ALLIANCE TOOLS … So please help me…

    Thanks & Regards
    RAMKI

  11. Avishek Sinha Roy says:

    hi ashwith,
    first of all thanx for the blog.
    whenever i am using “genpat filename” command no filename.pat file is generated. Is it supposed to be generated at the same file location of my input .c file? How do I know if my c program is without error or not? I have installed genpat successfully.

    • Ashwith says:

      Are you typing “genpat filename” or “genpat input”?

      You need to save the code in a file like test.c (the extension is required). But when running genpat, you need to run genpat test. So in your case, since you have named your file as input.c, you need to run genpat input.

  12. Avishek Sinha Roy says:

    thnx for the reply…actually i figured out the solution,i have to use “alliance-genpat input” to get it work , but now i am getting compilation error
    /usr/bin/ld: cannot find -lPgn
    /usr/bin/ld: cannot find -lPpt
    /usr/bin/ld: cannot find -lPhl
    /usr/bin/ld: cannot find -lPat
    /usr/bin/ld: cannot find -lMut
    /usr/bin/ld: cannot find -lRcn
    plz suggest how can i download the necessary file?

    • Ashwith says:

      Can you upload the file somewhere (say dropbox) and send me the link? I will take a look at it.

      One question, which operating system are you using? How did you install Alliance? The set up requires a couple of environment variables to be set otherwise it won’t work.

  13. Avishek Sinha Roy says:

    Hi ashwith,
    Thanks again for the reply. Actually there is a problem with the setting up of the environment variables as you have correctly mentioned. I have resolved the issue and its working properly.
    Can you kindly tell how to instantiate components in VHDL alliance and simulate it. For example i want to build a 4 bit full adder using 1 bit full adder.
    Thanks in advance.

  14. qwer says:

    i tried to simulate the simple behavioral code(MUX) using the command ASIMUT…Im getting the output pattern in the separete file(asimut -b mux mux_in mux_out)..but when i want to visualize input and output patterns using xpat & but its showing error as below.
    Parameters file /usr/etc/xpat.par can’t be opened

  15. Madhurani says:

    Hi,
    I got very good knowledge of simulation in Alliance. And me only tried synthesis. But I am unable to proceed further in pace and route. please reply soon about it as i need it .
    Thanks

    • Ashwith says:

      Unfortunately I’ve not progressed much in Alliance. Many things haven’t worked for me. Plus I’m better at Verilog so I’ve gone ahead with Icarus.

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