VHDL in Alliance – Behavioral Simulations

Hello everyone and welcome to the second tutorial on the Alliance VLSI package! πŸ™‚ Here we will look at how we can build a digital system using a behavioral model and simulate the VHDL code we write. I hope you have read the previous tutorial on genpat. We will need what ever we learn there to test the code we write in this tutorial. I also assume that you are familiar with VHDL. Alright then. Lets begin!

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VHDL in Alliance – A Different Start!

Welcome back! πŸ™‚ Its time to start off with Digital Design in VHDL using the Alliance package available in Fedora Electronic Lab. Now most tutorials would start of with the simulator itself. I have however, chosen a different start – The stimulus. The reason for this it that we need a stimulus for every simulation that we run in future tutorials and Alliance uses a separate file format for this. Read more of this post

Verilog & VHDL up Next! – Warming up

Hello everyone!

Posting after ages since I’ve been quite busy at work. But I haven’t forgotten about this blog :). As promised, I will deal with some tools on HDLs next – namely Icarus Verilog and the Alliance VLSI CAD system (which uses VHDL).

This post is basically to help you get geared up. Most probably you won’t even need a tutorial after this. ;). Oh and before I begin, I finally bought an Android phone last month. Its an HTC Wildfire πŸ™‚

Not as powerful as a Nexus and many phones out there but it was worth it. Has a nice camera, supports most of the apps on the market.

Alright back to why I’m posting. Here is a small description of the stuff we will look at in the forthcoming posts:

  • Icarus Verilog: A Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. (Source: http://spins.fedoraproject.org/fel/#portfolio Couldn’t open the official site for some reason :-|)
  • Alliance: Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. (Source: http://www-asim.lip6.fr/recherche/alliance/)

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My New Bike! :-)

That’s right! πŸ™‚ Its brand new Honda CB Twister. I had ordered it last week on Friday and it was due tomorrow but by my luck I ended up getting it yesterday itself. The twister is real light, comfortable and highly fuel efficient. Features include a 110cc Honda engine, front disc brakes, tubeless tires a mileage of 70 kmpl and some beautiful looks :). The suspensions work great as well. One down side however is that the wheels are real thin. Not good for the roads I see here :-|. Anyways I think its an awesome bike and worth the money. I leave you with some pics:

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Beautiful isn’t it? What do you think? Post a comment. Thanks for reading. See you next time πŸ™‚

Bruno The Simplest Line Follower – The Workshops :)

This post comes after I bumped into a video I should have posted along with the tutorial on this robot. As I said in that tutorial, the robot (I named it bruno later) was made for a workshop. This workshop was held two and a half years back and was a huge success considering the last minute planning and the limited help we had. Here is a video of me at the workshop which I happened to find on youtube today. Can’t believe I forgot this one. Here you go…

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Fedora 14 Installed! – Well not entirely…

After an extra day of waiting (wish I had a blazing fast net connection :(), I finally got a chance to look at Fedora’s 14th release myself. Here is the desktop screenshot:

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Fedora 14 Laughlin released

Its been a 6 month wait and its finally here – the Fedora Community released Fedora 14 Laughlin. Features of this release are:

  • Spice – Spice aims to provide a complete open source solution for interaction with virtualized desktops and provides high-quality remote access to QEMU virtual machines.
  • Mobility options – This release includes software from the MeeGoβ„’ project which is designed to support platforms such as netbooks, nettops, and various embedded devices.
  • Amazon EC2 – For the first time since Fedora 8, Fedora will release on the EC2 cloud.
  • D Compiler – Support for D, a systems programming language. Its focus is on combining the power and high performance of C and C++ with the programmer productivity of modern languages like Ruby and Python.

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ngspice – Interactive Mode!

Welcome back for the 5th tutorial on SPICE in Fedora Electronic Lab. πŸ™‚ This time we’ll look at ngspice’s interactive mode. We’ll see what this means in some time. Before that, make sure that you have gone through the previous tutorials. These are all filed under the SPICE category (point your mouse to Tutorials, then click SPICE). We will reuse the example circuits we created in the previous tutorials for this one. I hope you’ve gone through those first. We’ll begin with two circuits to show how some simple analysis can be done just like in batch mode. Finally we’ll end with an example which shows a great aspect of the interactive simulations – tweaking circuits automatically.

Before we begin any circuit, delete the SPICE include symbol from the schematic and get the netlist again. We do not need the cmd files now. Alternatively you could just open the netlist and delete the .INCLUDE line. We will be looking at the Bridge Rectifier, the BJT Amplifier andΒ  the op-amp non-inverting amplifier. Now lets begin πŸ™‚

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Breaking it down – The .SUBCKT

Having done so many simulation examples, ever wondered how complex actual circuits can be? When you go on to design a circuit with some application it won’t be just one amplifier or one rectifier. It’ll have dozens of blocks. How do you fit all that in one schematic? Well you can’t – at least not without getting totally mixed up with where each block is. Thats where hierarchical design comes in. This means that you break down a system into blocks. Break these blocks down even further till you get the simplest ones – like a tree branching out and having leaves at the end. The advantage of this is that most of the time, these “leaves” will repeat across your circuit and with a hierarchical design, these circuits need to be defined just once and reused again.

I hope you have read my previous tutorial on symbol creation in gschem as well as other tutorials on SPICE. You can get these tutorials by pointing your mouse to the Tutorials menu at the top and then selecting SPICE. You need the symbol of the previous tutorial to go through this one. Click Here to go to the symbols creation tutorial.

We will first look at a few op-amp circuits. I will be using LM741 for the examples. You can get the model (and many others) from Texas Instruments. Next we’ll build a two-stage BJT amplifier using a single BJT amplifier as a building block. Just like last time, I will explain only what is new. So lets begin, with my favorite part of analog circuits – operational amplifiers πŸ™‚

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Creating Your Own Symbols in gschem

Before writing another tutorial on SPICE, I thought of spending some time on creating symbols. This will be necessary because we will be looking at op-amp circuits next. There are op-amps in the gschem library but there are incompatibilities between those and the model files which the manufacturers provide. While trying to figure out how to create symbols, I found an excellent 3 part tutorial on this. I will take you through the creation of an op-amp symbol in this tutorial but I still feel this video will do better than that. Take a look at these before reading on:

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