Verilog & VHDL up Next! – Warming up

Hello everyone!

Posting after ages since I’ve been quite busy at work. But I haven’t forgotten about this blog :). As promised, I will deal with some tools on HDLs next – namely Icarus Verilog and the Alliance VLSI CAD system (which uses VHDL).

This post is basically to help you get geared up. Most probably you won’t even need a tutorial after this. ;). Oh and before I begin, I finally bought an Android phone last month. Its an HTC Wildfire 🙂

Not as powerful as a Nexus and many phones out there but it was worth it. Has a nice camera, supports most of the apps on the market.

Alright back to why I’m posting. Here is a small description of the stuff we will look at in the forthcoming posts:

  • Icarus Verilog: A Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. (Source: Couldn’t open the official site for some reason :-|)
  • Alliance: Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. (Source:

So before we begin, I would suggest brushing up with VHDL and Verilog (if, like me, you haven’t used them for a long time) and check out these resources:

  • Icarus Verilog User Guide: A documentation wiki – Very well explained.
  • Introduction to CMOS VLSI Circuits Design: An excellent openbook that covers all the tools in the Alliance package – very simple to understand.
  • The alliance-doc package: Install this by running “sudo yum install alliance-doc” (without quotes). Surprising it doesn’t come with Electronic Lab itself. The tutorial will be located in /usr/share/doc/alliance-doc-5.0/. Check it out. It explains everything beautifully as well.

I’m guessing if you read those, you won’t need tutorials but I thought I should give a few examples to show the process as a whole  (which I am still learning myself) and hopefully get one to learn to start using these tools quickly:

I’m sure you can’t wait. So here is a quick intro to Icarus Verilog! 🙂

First, a small snippet:

module half_adder(A, B, Sum, Cout);
  input   A;
  input   B;
  output  Sum;
  output  Cout;

  assign Sum  = A ^ B;
  assign Cout = A & B;

A simple half adder – save this to a file named half-adder.v. Now we need a testbench as well. So here is mine:

module test;

  reg A;
  reg B;
  wire Sum;
  wire Cout;

  half_adder hf1(.A(A), .B(B), .Sum(Sum), .Cout(Cout));

  initial begin
    $dumpvars(0, test);
    A = 0;
    B = 0;
#10 A = 0;
    B = 1;
#10 A = 1;
    B = 0;
#10 A = 1;
    B = 1;
#10 $finish;

Save this to half-adder-test.v. Now compile it using the command:

 iverilog -o half-adder half-adder.v half-adder-test.v

The -o switch lets you specify the output file name which in this case is half-adder. Now generate the vcd dump by running:

vvp half-adder 

VCD(Click for more info) is a format to store the output waveforms. Finally view the waveforms on gtkwave:

gtkwave half-adder-dump.vcd &

Here is a screenshot:

(Click the Image to enlarge)

And thats about it. Simple enough isn’t? Icarus was the first tool I learned on FEL and I feel it is the simplest verilog compiler and simulator out there. Try exploring yourself starting with the links at the beginning of this post. Catch you next time for my introduction to the Alliance package. Also please do comment with feedback and suggestions. Thanks for reading! 🙂

sudo yum install alliance-doc

2 Responses to Verilog & VHDL up Next! – Warming up

  1. Somebody out there says:

    One minor clarification. Icarus Verilog is a simulator rather than compiler. The old version 0.8.X had some synthesis support but rather limited. 0.9.x tree main focus is simulation and verilog 2005 support. If you want an open source logic synthesis tool (from verilog) – you need to have a look at tools such as VL2MV, VIS, SIS, ABC … Or maybe have a look at Logisim – it is incredibly cool app that people use to create microprocessor simulations – check it on youtube. 🙂

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