VHDL in Alliance – Behavioral Simulations

Hello everyone and welcome to the second tutorial on the Alliance VLSI package! :) Here we will look at how we can build a digital system using a behavioral model and simulate the VHDL code we write. I hope you have read the previous tutorial on genpat. We will need what ever we learn there to test the code we write in this tutorial. I also assume that you are familiar with VHDL. Alright then. Lets begin!

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VHDL in Alliance – A Different Start!

Welcome back! :) Its time to start off with Digital Design in VHDL using the Alliance package available in Fedora Electronic Lab. Now most tutorials would start of with the simulator itself. I have however, chosen a different start – The stimulus. The reason for this it that we need a stimulus for every simulation that we run in future tutorials and Alliance uses a separate file format for this. Read more of this post

Verilog & VHDL up Next! – Warming up

Hello everyone!

Posting after ages since I’ve been quite busy at work. But I haven’t forgotten about this blog :). As promised, I will deal with some tools on HDLs next – namely Icarus Verilog and the Alliance VLSI CAD system (which uses VHDL).

This post is basically to help you get geared up. Most probably you won’t even need a tutorial after this. ;). Oh and before I begin, I finally bought an Android phone last month. Its an HTC Wildfire :)

Not as powerful as a Nexus and many phones out there but it was worth it. Has a nice camera, supports most of the apps on the market.

Alright back to why I’m posting. Here is a small description of the stuff we will look at in the forthcoming posts:

  • Icarus Verilog: A Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. (Source: http://spins.fedoraproject.org/fel/#portfolio Couldn’t open the official site for some reason :-|)
  • Alliance: Alliance is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). Alliance has been used for research projects such as the 875 000 transistors StaCS superscalar microprocessor and 400 000 transistors IEEE Gigabit HSL Router. (Source: http://www-asim.lip6.fr/recherche/alliance/)

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